Re: Register allocation issues

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Register allocation issues
\ Matt Lee (5 Sep 2007)
. \ Ian Lance Taylor (6 Sep 2007)
. \ David Edelsohn (6 Sep 2007)
. . \ Matt Lee (6 Sep 2007)
. \ Dave Korn (6 Sep 2007)
. . \ Matt Lee (6 Sep 2007)
. \ dje (6 Sep 2007)
. . \ Matt Lee (6 Sep 2007)
. \ Segher Boessenkool (6 Sep 2007)
. . \ Matt Lee (6 Sep 2007)

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Subject:	Re: Register allocation issues
Group:	Gcc
From:	Matt Lee
Date:	6 Sep 2007

On 9/6/07, dje <dje> wrote:
> >>>>> Matt Lee writes:
> Date: Thu, 06 Sep 2007 15:02:52 -0400
> From: David Edelsohn <dje>
>
> Matt> There is no point trying to minimize usage of volatile hard registers,
> Matt> is there? They are precisely there to be used up as much as needed.
> Matt> The function is a leaf procedure as well, so there are no other
> Matt> considerations. Lastly, architectures like PPC do make use of more
> Matt> registers (without -frename-registers), so there has to be something
> Matt> in the PPC back-end that allows for the liberal use or in mine that
> Matt> prevents such.
>
> GCC RA mostly is tuned for IA-32 with very few registers.
>
> The rs6000 port defines the movmemsi pattern calling
> expand_block_move() which generates many intermediate pseudos.
>

So does mine. My generated RTL has all the right looking RTL with a
unique pseudo for each load/store pair. If you see the dump in the
original email from the .lreg files, the problem is that these pseudos
get bound to only 2 out of 10 candidate volatile registers.

--
thanks,
Matt