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andrew>> I've been thinking about this some more. I andrew>> suspect you could get good results by andrew>> generating not 8051 assembly language, andrew>> which would be gross, but a simple bytecode engine. I know this for a fact :-) in a previous life we modeled the one we did off the instruction set like the MIPS. Why? Simple - it has to do with the way the flags register is done. On some CPUs - when you add "r0 + r1" => r2, you either *must* update the flags (zero, carry, overflow) or not. having to maintain that in a simulator is added wasteful steps that you often do not need... For example the test: if( a == b ){ do_this(); } For us the opcodes became: test r1=r2 ;; test(r1==r2) braf +4 ; branch if false jsr24 do_this ; 24bit relative call. This simplified the interpretation code and was a huge performance win on a 6502 @ 1mhz. The simulation engine was a big 6502 switch statement. In effect, the 6502 was a micro-code engine :-) -Duane.
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